JPH0561715B2 - - Google Patents

Info

Publication number
JPH0561715B2
JPH0561715B2 JP62064671A JP6467187A JPH0561715B2 JP H0561715 B2 JPH0561715 B2 JP H0561715B2 JP 62064671 A JP62064671 A JP 62064671A JP 6467187 A JP6467187 A JP 6467187A JP H0561715 B2 JPH0561715 B2 JP H0561715B2
Authority
JP
Japan
Prior art keywords
signal
circuit
signal line
chip enable
sequential circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62064671A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63229691A (ja
Inventor
Yasushi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP62064671A priority Critical patent/JPS63229691A/ja
Priority to US07/169,683 priority patent/US4918657A/en
Publication of JPS63229691A publication Critical patent/JPS63229691A/ja
Publication of JPH0561715B2 publication Critical patent/JPH0561715B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Static Random-Access Memory (AREA)
JP62064671A 1987-03-18 1987-03-18 メモリ周辺回路 Granted JPS63229691A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62064671A JPS63229691A (ja) 1987-03-18 1987-03-18 メモリ周辺回路
US07/169,683 US4918657A (en) 1987-03-18 1988-03-18 Semiconductor memory device provided with an improved precharge and enable control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62064671A JPS63229691A (ja) 1987-03-18 1987-03-18 メモリ周辺回路

Publications (2)

Publication Number Publication Date
JPS63229691A JPS63229691A (ja) 1988-09-26
JPH0561715B2 true JPH0561715B2 (en]) 1993-09-06

Family

ID=13264876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62064671A Granted JPS63229691A (ja) 1987-03-18 1987-03-18 メモリ周辺回路

Country Status (2)

Country Link
US (1) US4918657A (en])
JP (1) JPS63229691A (en])

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208783A (en) * 1988-04-05 1993-05-04 Matsushita Electric Industrial Co., Ltd. Memory unit delay-compensating circuit
JPH03503812A (ja) * 1988-12-24 1991-08-22 アルカテル・エヌ・ブイ ２次元座標メモリ用非同期タイミング回路
US5799186A (en) * 1990-12-20 1998-08-25 Eastman Kodak Company Method and apparatus for programming a peripheral processor with a serial output memory device
US5325515A (en) * 1991-05-14 1994-06-28 Nec Electronics, Inc. Single-component memory controller utilizing asynchronous state machines
US5590088A (en) * 1993-07-13 1996-12-31 Seiko Epson Corporation Semiconductor memory device with enable signal conversion circuit operative for reducing current consumption
US6304921B1 (en) * 1998-12-07 2001-10-16 Motorola Inc. System for serial peripheral interface with embedded addressing circuit for providing portion of an address for peripheral devices

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3801827A (en) * 1972-10-05 1974-04-02 Bell Telephone Labor Inc Multiple-phase control signal generator
US4040122A (en) * 1976-04-07 1977-08-02 Burroughs Corporation Method and apparatus for refreshing a dynamic memory by sequential transparent readings
US4463440A (en) * 1980-04-15 1984-07-31 Sharp Kabushiki Kaisha System clock generator in integrated circuit
US4570082A (en) * 1983-11-25 1986-02-11 International Business Machines Corporation Single clocked latch circuit
US4755964A (en) * 1985-04-19 1988-07-05 American Telephone And Telegraph Company Memory control circuit permitting microcomputer system to utilize static and dynamic rams

Also Published As

Publication number Publication date
JPS63229691A (ja) 1988-09-26
US4918657A (en) 1990-04-17

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees